I. Field of the Invention
This invention relates to a junction type field effect transistor (abbreviated as "J-FET"), and more particularly to a multichannel type vertical J-FET displaying a triode characteristic.
II. Description of the Prior Art
To date, various forms of power supply type vertical J-FET have been proposed. However, the proposed J-FET's are accompanied with drawbacks, though possessed of some merits.
For instance, the Japanese Patent Application Publication No. 84181 (laid open to public on July 7, 1975) sets forth a J-FET admitting of an easy control of the width and depth of a channel section on which the property of the J-FET largely depends. The proposed J-FET comprises a semiconductor layer of one conductivity type and a plurality of annular insulation layers formed by selective oxidation to a prescribed depth from the surface of the semiconductor layer. A gate region of the opposite conductivity type to the semiconductor layer is formed in the semiconductor layer between the respective adjacent annular insulation layers. A source region is formed in that portion of the semiconductor layer which is surrounded by each annular insulation layer.
With the above-mentioned J-FET in which a source region is surrounded by an annular insulation layer, the depth and width of a channel section formed under the source region between the adjacent gate regions are defined only by the depth to which an impurity is diffused to constitute the gate region. The proposed J-FET is characterized by the structure in which the source region has a smaller depth than the annular insulation layer. It is assumed from this fact that said J-FET is devised to elevate a withstand voltage across the source and gate regions in view of a fully large space allowed between the source and gate regions.
From the property of a triode, however, the proposed J-FET cannot be regarded to have a fully satisfactory structure. Generally, a transistor can display a good triode property when a curve representing the voltage-current characteristic of the transistor is prevented as much as possible from presenting a saturated state. However, the proposed J-FET has the drawbacks that the voltage-current curve indicates a saturated state relatively early and moreover gate-leakage current increases.